1. Field of the Invention
The present invention relates to the power network of an integrated circuit (IC) and in particular to reducing congestion on the IC by removing power network stacked vias while ensuring that a target voltage drop is not exceeded and maintaining the connectivity of the original power network.
2. Related Art
As the power supply voltage level in industrial IC designs continues to scale down due to the continuing drive for low-power electronics, the noise introduced by voltage drop in the power (or ground) network becomes increasingly important. As a result, a dense power network may be required to minimize the voltage drop. This dense power network can include a large number of stacked vias created from the top-level power network all the way down to the standard cell rails. As used herein, a stacked via is defined as a plurality of vias connecting two metal lines in non-adjacent metal layers and having no intermediate, connecting metal lines. For example, FIG. 1 illustrates an exemplary stacked via 100 including three vias 101, 102, and 103. Stacked via 100 connects metal lines 104 and 105 (which are formed in different metal layers) and have no intermediate, connecting metal lines (i.e. the interface between vias 101 and 102 has no connection to a metal line; similarly, the interface between vias 102 and 103 has no connection to a metal line).
Unfortunately, the use of stacked vias may cause congestion on an IC. For example, FIG. 2 illustrates an exemplary top view of one via layer of a power network 200 including a plurality of vias 201 (three labeled for illustration purposes), all of which represent the locations of stacked vias. In an actual power network, numerous stacked vias could be included, which along with components of the IC design (not shown for simplicity in relation to the via layer), could easily result in congestion. Conventional approaches to reducing this congestion have distinct disadvantages.
For example, increasing the die size of the IC can reduce congestion, but incurs higher cost and longer turn-around time. Uniformly removing stacked vias every other N rows/columns (where N is a predetermined integer greater than 1) can also reduce congestion, but may incur higher voltage drop and loss of power network connectivity. Replacing normal vias with smaller vias having fewer cuts can also reduce congestion, but may incur higher voltage drop and higher electro-migration. (Note that a via includes one or more cuts (i.e. holes) therein that are filled with metal to connect the two metal lines. As the metal lines get wider, typically more cuts are provided in the via, thereby essentially forming a via array from the one “via”. Decreasing the number of cuts undesirably increases the resistance of such a via.) Manually removing stacked vias in congestion hot spots can also reduce congestion, but may incur higher voltage drop, the loss of power network connectivity, and longer turn-around time.
Therefore, a need arises for a technique of reducing congestion on an IC while meeting the voltage drop requirement, guaranteeing no loss of power network connectivity, and minimizing turn-around time.